1. Field of the Invention
The present invention relates to a semiconductor device provided with a high voltage transistor, particularly, to a semiconductor device having a high degree of integration and a method of manufacturing the same.
2. Description of the Related Art
The construction of a conventional nonvolatile semiconductor memory device will now be described with reference to FIGS. 21 and 22. FIG. 21 is a cross sectional view showing the construction of the cell portion and the peripheral circuit portion of a NOR type flash memory.
As shown in FIG. 21, the NOR type flash memory comprises a high voltage transistor 203 used for writing, reading and erasing information in a memory cell 202 and a low voltage transistor 204 in addition to the memory cell 202 formed of a stacked transistor including a stacked gate structure having a floating gate 200 having a memory retaining capability and a control gate 201.
The memory cell 202 is constructed such that a gate structure is interposed between source/drain diffusion layers 214. The gate structure has a stacked gate structure including a tunnel oxide film 218 formed on a semiconductor substrate 223, the floating gate 200 formed on the tunnel oxide film 218, an interlayer insulating film 219 formed on the floating gate 200, and the control gate 201 formed on the interlayer insulating film 219. Further, a gate side wall 209b is formed in a manner to surround the stacked gate structure noted above. Incidentally, the memory cell 202 is separated from the memory peripheral element such as a high voltage transistor by a shallow trench isolation layer 221.
The high voltage transistor 203 is constructed such that a gate structure is interposed between two N− type diffusion layers 206 formed in the surface region of the substrate 223. The gate structure noted above includes a thick gate oxide film 205 formed on the semiconductor substrate 223 and a gate electrode 211 formed on the gate oxide film 205. A gate side wall 209 equal in thickness to the gate side wall 209b of the memory cell 202 is formed to surround the gate structure, and the surface region of the N− diffusion layer 206 is covered with the gate insulating film 205 and the gate side wall 209. Further, N+ diffusion layers 207 are formed to extend away from the gate structure on those portions of the surface of the substrate 223 which are positioned outside the N− diffusion layers 206.
Further, the low voltage transistor 204 referred to previously is formed away from the high voltage transistor 203, with a shallow trench isolation layer 221 interposed therebetween. In the low voltage transistor 204, a gate electrode is formed between adjacent N− diffusion layers 216. The gate structure comprises a thin gate oxide film 220 formed on the semiconductor substrate 223 and a gate electrode 212 formed on the gate oxide film 220. A side wall 209a equal in thickness to the memory cell 202 is formed to surround the gate structure of the transistor 204. Further, N+ diffusion layers 215 are formed to extend from the N− diffusion layers 216 to the outside of the gate structure.
The high voltage transistor 203 is used for supplying a high voltage of ten and several volts to the memory cell 202 for the operation of, for example, writing and erasing information. In the high voltage transistor 203, the gate oxide film 205 has a large thickness, e.g., 20 nm, in order to prevent the gate oxide film 205 from being subjected to the insulation breakdown under a high voltage. In addition, it is necessary to set the junction breakdown voltage of the source/drain diffusion layers 206 and 207 at a high value of ten and several volts.
Under the circumstances, the diffusion layer 206 having a low concentration of N-type (P-type) impurity is formed deep. At the same time, a distance 208 (hereinafter referred to as an LDD length 208) of the tip of the diffusion layer 206 having a low concentration of the N-type (P-type) impurity, the tip being positioned below the gate insulating film 205 and the gate side wall 209, from the boundary between the diffusion layer 207 having a high concentration of an N-type (P-type) impurity and the diffusion layer 206 having a low impurity concentration noted above is set at a large value so as to facilitate the expansion of the depletion layer within the diffusion layer 206 having a low impurity concentration, thereby increasing the junction breakdown voltage.
Particularly, in the case of the high voltage transistor 203 is of a PMOS transistor, a P-type impurity of boron tends to be diffused into the semiconductor substrate 223 by the various heating steps employed in the process between the formation of the diffusion layers 206, 207 and the completion of the semiconductor device. Therefore, unless the thickness of the gate side wall 209 determining the LDD length 208 is maintained at a level not lower than a certain level, the LDD length 208 of the low impurity concentration region 206 positioned below the gate insulating film 205 and the gate side wall 209 is shortened or tends to be eliminated by the diffusion of boron from the high impurity concentration region 207 into the low impurity concentration region 206.
On the other hand, in a high voltage NMOS transistor (not shown), an N-type impurity of arsenic has a degree of diffusion in the heating step lower than that of the P-type impurity of boron so as to make it possible to form the gate side wall in a thickness smaller than that for the PMOS transistor 203.
However, in the conventional LDD structure shown in FIG. 21, the gate side wall 209 has a large thickness, e.g., 0.2 μm. The thickness of the gate side wall 209 is determined to conform with the PMOS transistor 203 requiring a high breakdown voltage. It follows that the gate side walls 209b and 209a of the memory 202 and the transistor 204 have thicknesses conforming with the high voltage PMOS transistor 203.
The ion implantation of a low concentration of a P-type impurity in the high voltage transistor 203 is performed after formation of the gate electrode 211, followed by forming the gate side wall 209. It is possible to set the LDD length 208 at a large value if the ion implantation of a P-type impurity is performed, after formation of the gate side wall 209, for forming the P+ diffusion layer 207 with the gate side wall 209 used as a mask. In the prior art, each of the side wall 209a of the low voltage transistor 204 and the side wall 209b of the memory cell 202 is formed in a large thickness of about 0.2 μm like the side wall of the high voltage transistor 203. What should be noted is that, in the prior art, the side walls 209b, 209 and 209a of the memory cell 202, and the transistors 203 and 204, respectively, are uniformly formed in the same thickness so as to decrease the number of process steps by forming simultaneously the side walls of the memory cell 202 and the transistors 203 and 204 in the same manufacturing process.
It should be noted that the distance between a contact hole 210 of the memory cell 202 and the gate electrode 201, the distance between a contact hole 210 of the transistor 203 and the gate electrode 203, and the distance between a contact hole 210 of the of the transistor 203 and the gate electrode 212 are equal to the sum of, for example, a side wall thickness 224 of the high voltage transistor 203 and an aligning allowance 225 between the side wall 209 and the contact hole 210. The aligning allowance is determined by the accuracy in the deviation of the alignment between the contact hole 210 and a gate electrode 211, the accuracy of the size in the contact hole 210 itself, and the accuracy of the size in the gate electrode 211 itself. This is also the case with the other memory cell 202 and the transistor 204.
Japanese Patent Application No. 11-46728 filed by the same assignee of the present application also discloses a semiconductor device relevant to the present application. This prior art will now be described with reference to FIG. 22. Incidentally, those portions of FIG. 22 which are equal to FIG. 21 are denoted by the same reference numerals so as to avoid an overlapping description.
In the prior art shown in FIG. 22, two kinds of the gate side wall structures are used for the memory cell and the transistors, including a thick gate side wall 112 used in the high voltage transistor 203 and a thin gate side wall 114 having a predetermined thickness 115, which is used in each of the memory cell 202 and the low voltage transistor 204. The first gate side wall 112 of the high voltage transistor 203 has a predetermined thickness 120 larger than the thickness 115 of the gate side wall 114 of the memory cell 202 and the low voltage transistor 204. Further, a second side wall 111 is formed in an upper portion of the first gate side wall 112.
In the case of employing the structure shown in FIG. 22, it is possible to ensure a sufficient LDD length 116, which permits obtaining the required junction breakdown voltage, in the high voltage transistor 203. It is also possible to use the side wall 114 thinner than that in the prior art shown in FIG. 21 in each of the memory cell 202 and the low voltage transistor 204. What should also be noted is that, since the LDD length 117 in the low voltage transistor 204 is smaller than the LDD length 116 of the high voltage transistor 203, it is possible to diminish the distance 119 between the gate electrode 212 and the contact hole 210.
The distance 119 is a sum of the side wall thickness 115 and the aligning allowance 225. In the high voltage transistor 203, the distance 118 between the gate electrode 211 and the contact hole 210 is equal to the sum of the side wall thickness 120 of the high voltage transistor 203 and the aligning allowance 225, which is larger than the distance 119 between the gates 200, 201, 212 and the contact hole 210 in the memory cell 202 and the low voltage transistor 204, respectively.
Further, FIG. 1 of Japanese Patent Disclosure (Kokai) No. 8-23031 discloses a semiconductor integrated circuit in which a double layer structure is employed in the gate side wall in order to increase the withstand voltage of the high voltage MOS transistor and to improve the driving capability of the low voltage MOS transistor. In this prior art, a diffusion layer of a high impurity concentration is formed with respect to the outer layer of the gate side wall having a double layer structure on the side of the high voltage MOS transistor, and a diffusion layer of a high impurity concentration is formed with respect to the inner layer of the gate side wall having a double layer structure on the side of the low voltage MOS transistor.
The method of manufacturing the conventional semiconductor device shown in FIG. 21 gives rise to the problem pointed out below.
Specifically, in forming the contact hole 210, there is a possibility for the contact hole 210 to be formed close to each of the gate electrodes 201, 211 and 212 because of the deviation in the mask alignment. There is also a possibility to bring about the inconvenience that the contact hole 210 is caused to deviate to cover partly the gate side walls 209a, 209 and 209a because of the enlargement in the size of these members. Where the material forming the gate side wall is unlikely to be etched, the bottom surface of the contact hole 210 fails to be brought into contact with the surface of the diffusion region formed in the surface region of the semiconductor substrate 223 as designed. Since the contact area between the bottom surface of the contact hole 210 and the surface of the substrate 223 is diminished, the contact resistance of the contact hole 210 is increased.
On the other hand, where the semiconductor device is designed such that a sufficient distance, e.g., 0.2 μm, is provided between the contact hole 210 and each of the gate side walls 209b, 209 and 209a so as to prevent the contact hole 210 from being brought into contact with any of the gate side walls 209b, 209, 209a, the distance between the contact hole 210 and each of the gate electrodes 201, 211 and 212 is rendered large, e.g., 0.4 μm, leading to an increase in the chip size.
Concerning the memory cell 202, the N+ diffusion layers 214 are formed as the source/drain regions in a manner to overlap partly with the floating gate 200, with the result that the LDD side wall structure 209b is originally unnecessary. It should be noted in this connection that, in forming the LDD structure for the peripheral transistors during the manufacturing process of the semiconductor device, the gate side wall 209b is also formed simultaneously in the memory cell 202, with the result that the gate side wall is also present in the memory cell 202.
However, if the memory cell 202 is made finer so as to make smaller the distance between the adjacent word lines connected to the memory cells, the area of the bottom surface of the contact hole 210 is made very small or is eliminated completely by the thick gate side wall 209b so as to make it impossible to design the semiconductor device such that a contact is formed between the adjacent word lines. Such being the situation, in order to form a contact hole between the adjacent word lines, it is unavoidable to enlarge the cell size because the side wall is thick. This is a very serious problem inhibiting the miniaturization of the semiconductor device.
A serious problem also remains unsolved in the low voltage NMOS transistor 204 of the peripheral circuit. Specifically, since the side wall 209a is rendered thick, the LDD length 217 of the N− diffusion layer 216 is rendered long so as to increase the parasitic resistance, leading to the problem that the current driving capability of the transistor 204 is lowered.
Under the circumstances, since a high junction breakdown voltage is unnecessary in the low voltage transistor 204, the inconvenience is brought about that the circuit pattern is rendered large and the performance is deteriorated.
The prior art shown in FIG. 22 is capable of resolving the problem inherent in the prior art shown in FIG. 21. In the prior art shown in FIG. 22, however, the thick gate side wall 112 is formed in only the high voltage transistor 203 and, thus, the gate side walls 112 and 114 are formed separately by adding one or two photolithography steps to the prior art shown in FIG. 21. It follows that the gate side wall forming steps are rendered complex, leading to an increase in the number of manufacturing steps, compared with the prior art shown in FIG. 21.